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nb675 24v, high current synchronous buck converter with +/-1.5a ldo and buffed reference nb675 rev. 1.0 www.monolithicpower.com 1 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the nb675 provides a complete power supply for ddr3, ddr3l and lpddr2 memory with the highest power density. it integrates a high frequency synchronous rectified step-down switch mode converter (vddq) with an 1.5a sink/source ldo (vtt) and buffered low noise reference (vttref). the fully integrated buck converter is able to deliver 10a continuous output current and 12a peak output current over a wide input supply range with excellent load and line regulation. the buck converter employs the constant-on- time (cot) control scheme, which provides fast transient response and eases loop stabilization. the vtt ldo provides 1.5a sink/source current capability and requires only 10uf ceramic capacitance. the vttref tracks vddq/2 with an excellent 1% accuracy. under voltage lockout is internally set as 4.5v. an open drain power good signal indicates vddq is within its nominal voltage range. full protection features include ocp, ovp, and thermal shut down. this part requires minimum number of external components and is available in qfn21 (3mmx4mm) package. features ? wide 5v to 24v operating input range ? 10a continuous output current ? 12a peak output current ? built-in +/- 1.5a vttldo ? low r ds (on) internal power mosfets ? proprietary switching loss reduction technique ? internal soft start ? output discharge ? 500khz switching frequency ? ocp, ovp, uvp protection and thermal shutdown ? vddq adjustable from 0.604v to 5.5v applications ? laptop computer ? tablet pc ? networking systems ? server ? personal video recorders ? flat panel television and monitors ? distributed power systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application en 1 fb bst vin pg sw en 2 nb675 pgnd vddq vcc vinldo vddqsen vtt vttsen agnd vttref vtt v in 5-21v 1.35v/10a 0.675v/2a 220nf 220nf load current (a) 15 25 35 45 55 65 75 85 95 0.001 0.01 0.1 1 10
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 2 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number* package top marking NB675GL qfn21 (3mmx4mm) nb675 * for tape & reel, add suffix ?z (e.g. NB675GL?z) package reference top view 6 58 9 pgnd 10 3 2 sw sw 17 18 16 14 nc en2 pgnd 11 agnd fb vinldo vddqsen vttsen vcc 13 pg 4 vttref 1 bst vin 12 15 7 vtt en1 exposed pad on backside 19 vin 20 pgnd 21 pgnd absolute maxi mum ratings (1) supply voltage v in ....................................... 24v v sw ...............................................-0.3v to 24.3v v sw (30ns)..........................................-3v to 28v v sw (5ns)............................................-6v to 28v v bst ................................................... v sw + 5.5v v en ............................................................... 12v enable current i en (2) ................................ 2.5ma all other pins ..............................?0.3v to +5.5v continuous power dissipation (t a =+25 ) (3) qfn21 ..................................................... 2.5w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (4) supply voltage v in ..............................5v to 22v output voltage v out ....................0.604v to 5.5v enable current i en ....................................... 1ma operating junction temp. (t j ). -40c to +125c thermal resistance (5) ja jc qfn21 (3mmx4mm) ...............50 ...... 12 ... c/w notes: 1) exceeding these ratings may damage the device. 2) refer to page 13 of configuring the en control. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operating conditions. 5) measured on jesd51-7, 4-layer pcb.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 3 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v in = 12v, t j = 25 c, unless otherwise noted. parameters symbol condition min typ max units supply current supply current (shutdown) i in v en = 0v 0 1 a supply current (in s0 mode) i in v en1 = v en1 = 2v, v fb = 0.65v, i vtt = 0a 300 400 500 a supply current (in s3 mode) i in v en1 = 0v, v en2 = 2v, v fb = 0.65v 160 190 220 a mosfet high-side switch on resistance hs rds-on t j =25 c 25 m ? low-side switch on resistance ls rds-on t j =25 c 9 m ? switch leakage sw lkg v en = 0v, v sw = 0v 0 1 a current limit low-side valley current limit i limit 10 11 12 a switching frequency and minimum off time switching frequency f s 400 500 600 khz minimum off time (6) t off 250 300 350 ns over-voltage and under-voltage protection ovp threshold v ovp 125 130 135 %v ref ovp delay t ovpdel 2.5 s uvp threshold v uvp 55 60 65 %v ref uvp delay t uvpdel 12 s reference and soft start reference voltage v ref 598 604 610 mv feedback current i fb v fb = 0.604v 10 50 na soft start time t ss 1.6 1.95 ms enable and uvlo enable input low voltage vil en 1.15 1.25 1.35 v enable hysteresis v en-hys 100 mv v en = 2v 3 enable input current i en v en = 0v 0 a vcc under voltage lockout threshold rising vcc vth 4.5 4.85 v vcc under voltage lockout threshold hysteresis vcc hys 500 mv
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 4 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t j = 25 c, unless otherwise noted. parameters symbol condition min typ max units vcc regulator vcc regulator v cc 4.8 5.1 5.3 v vcc load regulation icc=8ma 5 % power good fb rising (good) pg vth-hi 95 fb falling (fault) pg vth-lo 85 fb rising (fault) pg vth-hi 115 fb falling (good) pg vth-lo 105 %v ref power good low to high delay pg td 450 s power good sink current capability v pg sink 4ma 0.4 v power good leakage current i pg_leak v pg = 3.3v 1 a vttref output vttref output voltage v ttref v ddqsen /2 i vttref <0.1ma, 1v nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 5 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin functions pin # name description 1 bst bootstrap. a capacitor connected between sw and bst pins is required to form a floating supply across the high-side switch driver. 2, 3 sw switch output. connect this pin to the i nductor and bootstrap capacitor. this pin is driven up to the vin voltage by the high-si de switch during the on-time of the pwm duty cycle. the inductor current drives the sw pin negative during the off-time. the on- resistance of the low-side switch and the internal diode fixes the negative voltage. use wide and short pcb traces to make the connection. try to minimize the area of the sw pattern. 4 vttref buffered vtt reference output. decouple with a minimum 0.22 f ceramic capacitor as close to the pin as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 5 vddqsen buck regulator output voltage sense. connect th is pin to the output capacitor of the regulator directly 6 vinldo vtt ldo regulator input. connect vinldo to vddq in typical application. 7 vtt vtt ldo output. decouple with a minimum 10uf ceramic capacitor as close to the pin as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 8 agnd analog ground. the internal reference is referred to agnd. connect the gnd of the fb divider resistor to agnd for better load regulation. 9 vttsen vtt output sense. connect this pin to the output capacitor of t he vtt regulator directly 10,11 exposed pad 20,21 pgnd power ground. use wide pcb traces and multiple vias to make the connection. 12 exposed pad 19 vin supply voltage. the vin pin supplies power for internal mosfet and regulator. the nb675 operate from a +5v to +22v input rail. an input capacitor is needed to decouple the input rail. use wide pcb traces and mu ltiple vias to make the connection. 13 pg power good output, the output of this pin is an open drain signal and is high if the output voltage is higher than 95% of the nom inal voltage. there is a delay from fb 95% to pg goes high. 14 fb feedback. an external resistor divider from the output to gnd, tapped to the fb pin, sets the output voltage. place the resistor divider as close to fb pin as possible. a void vias on the fb traces. it is recommend to set the current through fb resistors around 10ua. 15 en1 enable. en1 and en2 are digital inputs, which are used to enable or disable the internal regulators. once en1=en2=1, the vddq regulator, vtt ldo and vttref output will be turned on; when en1=0 and en2=1, the vddq regulator and vttref are active while vtt ldo is off; all the r egulators will be turned off when en1=en2=0. 16 vcc internal 5v ldo output. the driver and cont rol circuits are powered from this voltage. decouple with a minimum 1f ceramic capacitor as close to the pin as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 17 en2 enable. en1 and en2 are digital inputs, which are used to enable or disable the internal regulators. once en1=en2=1, the vddq regulator, vtt ldo and vttref output will be turned on; when en1=0 and en2=1, the vddq regulator and vttref are active while vtt ldo is off; all the r egulators will be turned off when en1=en2=0. 18 nc not connected.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 6 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v in =20v, v ddq =1.35v, l=1.2h, t j =+25c, unless otherwise noted. 500 502 504 506 508 510 512 514 516 518 520 -50 0 50 100 150 power loss (mw) load regulation i_v_limit vs. temperature load current (a) load current (a) i_limit load current (a) switching frequency vs. temperature i out =5a frequency (khz) 11 11.2 11.4 11.6 11.8 12 12.2 12.4 12.6 12.8 13 -40 10 60 110 v tt sink current (ma) v tt source current (m a) voltage (v) voltage (v) 0 100 200 300 400 500 600 0246810 v tt ldo sink current load regulation v ddq =1.35v, v tt =v ddq /2 vtt ldo source current load regulation v ddq =1.35v, v tt =v ddq /2 output current (a) switching frequency vs. output current i out =10a frequency (khz) 15 25 35 45 55 65 75 85 95 0.001 0.01 0.1 1 10 0 500 1000 1500 2000 2500 3000 3500 01 234 5678910 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 01234 567 8910 v in =19v v in =12.6v v in =12.6v v in =19v v in =8.4v v in =8.4v v in =6v v in =12.6v v in =19v v in =6v v in =8.4v v in =6v 0.625 0.635 0.645 0.655 0.665 0.675 0.685 0.695 0.705 0.715 0.725 0 500 1000 1500 v tt v ttref 0.625 0.635 0.645 0.655 0.665 0.675 0.685 0.695 0.705 0.715 0.725 0 500 1000 1500 v ttref v tt
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 7 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =20v, v ddq =1.35v, l=1.2h, t j =+25c, unless otherwise noted. output voltage ripple i out = 0a output voltage ripple i out = 10a v ddq 500mv/div. v en2 5v/div. v pg 5v/div. i l 1a/div. v ddq 50mv/div. v sw 10v/div. i l 1a/div. v ddq 50mv/div. v sw 10v/div. i l 10a/div. v ddq 500mv/div. v en2 5v/div. v pg 5v/div. i l 10a/div. v ddq 500mv/div. v in 10v/div. v sw 10v/div. i l 5a/div. power good through en start-up i out = 0a power good through en start-up i out = 10a v ddq 500mv/div. v sw 10v/div. v in 10v/div. i l 10a/div. v en2 5v/div. v sw 20v/div. v ddq 1v/div. i l 2a/div. v ddq 1v/div. v sw 2v/div. v in 10v/div. i l 2a/div. v ddq 1v/div. v sw 5v/div. v in 5v/div. i l 5a/div. start-up through v in i out = 0a start-up through v in i out = 10a shutdown through v in i out = 0a shutdown through v in i out = 10a start-up through en i out = 0a
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 8 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =20v, v ddq =1.35v, l=1.2h, t j =+25c, unless otherwise noted. v ddq 1v/div. v en2 5v/div. v sw 20v/div. i l 10a/div. v ddq(ac) 20mv/div. i l 5a/div. v ddq 1v/div. v ttref 500mv/div. v tt 500mv/div. v in 20v/div. v ddq 500mv/div. v ttref 500mv/div. v tt 500mv/div. v in 10v/div. v ddq 1v/div. v ttref 500mv/div. v tt 500mv/div. v en1 5v/div. v ddq 1v/div. v ttref 500mv/div. v tt 500mv/div. v en1 2v/div. v ddq 1v/div. v ttref 500mv/div. v tt 500mv/div. v en2 5v/div. v ddq 1v/div. v en2 5v/div. v sw 5v/div. i l 2a/div. v ddq 1v/div. v en2 5v/div. v sw 20v/div. i l 10a/div.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 9 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =20v, v ddq =1.35v, l=1.2h, t j =+25c, unless otherwise noted. v out 500mv/div. i l 5a/div. v cc 2v/div. v sw 10v/div. v out 500mv/div. i l 5a/div. v cc 2v/div. v sw 10v/div. v ddq 1v/div. v ttref 500mv/div. v tt 500mv/div. v en2 5v/div. v ddq 1v/div. v in 500mv/div. v sw 10v/div. i l 10a/div.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 10 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. block diagram gate contr ol logic on time one shot fault logic soft- start por & reference 0.6v v ref 1v 130% vref ovp ocp pok uvp min off time fb 95 % vref 60% vref vddq vin sw bstreg vin bst sw pgnd pg vddqsen vcc agnd vtt vinldo control logic vttsen vttref en1/ en2 en1/ en2 figure 1?functional block diagram
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 11 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation pwm operation the nb675 is fully integrated synchronous rectified step-down switch mode converter. constant-on-time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ), which indicates insufficient output voltage. the on period is determined by both the output voltage and input voltage to make the switching frequency fairy constant over input voltage range. after the on period elapses, the hs-fet is turned off, or becomes off state. it is turned on again when vfb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize the conduction loss. there will be a dead short between input and gnd if both hs-fet and ls-fet are turned on at the same time. it?s called shoot-through. in order to avoid shoot-through, a dead-time (dt) is internally generated between hs-fet off and ls- fet on, or ls-fet off and hs-fet on. an internal compensation is applied for cot control to make a more stable operation even when ceramic capacitors are used as output capacitors, this internal compensation will then improve the jitter performance without affect the line or load regulation. heavy-load operation figure 2?heavy load operation when the output current is high and the inductor current is always above zero amps, it is called continuous-conduction-mode (ccm). the ccm mode operation is shown in figure 2 shown. when v fb is below v ref , hs-mosfet is turned on for a fixed interval which is determined by one- shot on-timer as equation 1 shown. when the hs-mosfet is turned off, the ls-mosfet is turned on until next period. in ccm mode operation, the switching frequency is fairly constant and it is called pwm mode. light-load operation with the load decrease, the inductor current decrease too. once the inductor current touch zero, the operation is transition from continuous- conduction-mode (ccm) to discontinuous- conduction-mode (dcm). the light load operation is shown in figure 3. when v fb is below v ref , hs-mosfet is turned on for a fixed interval which is determined by one- shot on-timer as equation 1 shown. when the hs-mosfet is turned off, the ls-mosfet is turned on until the inductor current reaches zero. in dcm operation, the v fb does not reach v ref when the inductor current is approaching zero. the ls-fet driver turns into tri-state (high z) whenever the inductor current reaches zero. a current modulator takes over the control of ls- fet and limits the inductor current to less than - 1ma. hence, the output capacitors discharge slowly to gnd through ls-fet. as a result, the efficiency at light load condition is greatly improved. at light load condition, the hs-fet is not turned on as frequently as at heavy load condition. this is called skip mode. at light load or no load condition, the output drops very slowly and the nb675 reduces the switching frequency naturally and then high efficiency is achieved at light load. figure 3?light load operation
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 12 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. as the output current increases from the light load condition, the time period within which the current modulator regulates becomes shorter. the hs-fet is turned on more frequently. hence, the switching frequency increases correspondingly. the output current reaches the critical level when the current modulator time is zero. the critical level of the output current is determined as follows: in out out out sin (v v ) v i 2lf v ? = (1) it turns into pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range. jitter and fb ramp slope jitter occurs in both pwm and skip modes when noise in the v fb ripple propagates a delay to the hs-fet driver, as shown in figures 4 and 5. jitter can affect system stability, with noise immunity proportional to the steepness of v fb ?s downward slope. however, v fb ripple does not directly affect noise immunity. v re f v fb hs dr i ver v noise jitter v slo pe1 figure 4?jitter in pwm mode v fb hs dr i ver jitter v ref v slo pe2 v noise figure 5?jitter in skip mode operating without external ramp the traditional constant-on-time control scheme is intrinsically unstable if output capacitor?s esr is not large enough as an effective current-sense resistor. ceramic capacitors usually can not be used as output capacitor. to realize the stability, the esr value should be chosen as follow: sw on esr out tt 0.7 2 r c + (2) t sw is the switching period. the nb675 has built in internal ramp compensation to make sure the system is stable even without the help of output capacitor?s esr; and thus the pure ceramic capacitor solution can be applicant. the pure ceramic capacitor solution can significantly reduce the output ripple, total bom cost and the board area. figure 6 shows a typical output circuit in pwm mode without an external ramp circuit. turn to application information section for design steps without external compensation. r1 r2 cap sw fb vo l c4 figure 6?simplified circuit in pwm mode without external ramp compensation when using a large-esr capacitor on the output, add a ceramic capacitor with a value of 10uf or less to in parallel to minimize the effect of esl. operating with external ramp compensation the nb675 is usually able to support ceramic output capacitors without external ramp, however, in some of the cases, the internal ramp may not be enough to stabilize the system, and external ramp compensation is needed. skip to application information section for design steps with external ramp compensation.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 13 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. r1 r2 ceramic sw fb vo l r4 c4 i r4 i c4 i fb r9 figure 7?simplified circuit in pwm mode with external ramp compensation figure 7 shows a simplified external ramp compensation (r4 and c4) for pwm mode, with hs-fet off. chose r1, r2, r9 and c4 of the external ramp to meet the following condition: 12 9 sw 4 1 2 rr 11 r 2f c 5 rr ?? < + ?? + ?? (3) where: r4 c4 fb c4 iiii =+ (4) and the vramp on the v fb can then be estimated as: in out 12 ramp on 44 12 9 vv r//r vt rc r//rr ? = + (5) the downward slope of the v fb ripple then follows ? ? == out ramp slope1 off 4 4 v v v trc (6) as can be seen from equation 6, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation 3, then we can only reduce r4. for a stable pwm operation, the v slope1 should be design follow equation 7. sw on -3 esr out slope1 out out sw on tt +-rc io 10 0.7 2 -v v + 2lc t -t (7) io is the load current. in skip mode, the downward slope of the v fb ripple is the same whether the external ramp is used or not. figure 8 shows the simplified circuit of the skip mode when both the hs-fet and ls- fet are off. r1 r2 esr cout fb vo ro figure 8?simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follow: () ref slope2 12 out v v (r r //ro) c ? = + (8) where ro is the equivalent load resistor. as described in figure 5, v slope2 in the skip mode is lower than that is in the pwm mode, so it is reasonable that the jitter in the skip mode is larger. if one wants a system with less jitter during light load condition, the values of the v fb resistors should not be too big, however, that will decrease the light load efficiency. when using a large-esr capacitor on the output, add a ceramic capacitor with a value of 10uf or less to in parallel to minimize the effect of esl. configuring the en control the nb675 has two enable pins to control the on/off of the internal regulators. all of vddq, vttref and vtt are turned on at s0 state (en1=en2=high). in s3 mode (en1=low, en2=high), vddq and vttref voltages are kept on while vtt is turned off and left at high impedance state (high-z). the vtt output floats and doesn?t sink/source current in this state. in s4/s5 mode (en1=en2=low), all of the regulators are kept off and discharged to gnd. table 1?en1/en2 control state en1 en2 vddq vttref vtt s0 high high on on on s3 low high on on off(high-z) s4/s5 low low off off off others high low off off off for automatic start-up the en pin can be pulled up to input voltage through a resistive voltage divider. choose the values of the pull-up resistor (r up from vin pin to en pin) and the pull-down
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 14 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. resistor (r down from en pin to gnd) to determine the automatic start-up voltage: up down in start down rr v1.45 (v) r ? + = (9) for example, for r up =150k ? and r down =51k ? ,the ? in start v is set at 5.52v. to avoid noise, a 10nf ceramic capacitor from en to gnd is recommended. there is an internal zener diode on the en pin, which clamps the en pin voltage to prevent it from running away. the maximum pull up current assuming a worst case 12v internal zener clamp should be less than 1ma. therefore, when en is driven by an external logic signal, the en voltage should be lower than 12v.when en is connected with vin through a pull-up resistor or a resistive voltage divider, the resistance selection should ensure the maximum pull up current less than 1ma. if using a resistive voltage divider and vin higher than 12v, the allowed minimum pull-up resistor r up should meet the following equation: in up down v(v) 12 12 1( m a ) r(k) r (k) ? ?< ? (10) especially, just using the pull-up resistor r up (the pull-down resistor is not connected), the in-start v is determined by input uvlo, and the minimum resistor value is: in up v(v) 12 r(k) 1( m a ) ? > (11) a typical pull-up resistor is 100k ? . soft start the nb675 employs soft start (ss) mechanism to ensure smooth output during power-up. when the en pin becomes high, the internal reference voltage ramps up gradually; hence, the output voltage ramps up smoothly, as well. once the reference voltage reaches the target value, the soft start finishes and it enters into steady state operation. if the output is pre-biased to a certain voltage during startup, the ic will disable the switching of both high-side and low-side switches until the voltage on the internal reference exceeds the sensed output voltage at the fb node. vtt and vttref this part integrates two high performance, low- drop-out linear regulators, vtt and vttref, to provide complete ddr3/ddr3l power solutions. the vttref has a 10-ma sink/source current capability, and track 1/2 of vddqsen using an on-chip divider. a minimum 0.22 f ceramic capacitor must be connected close to the vttref terminal for stable operation. the vtt regulator responses quickly to track vttref with +/-45mv under all conditions. the current capability of the vtt regulator is up to 1.5a for both sink and source modes. a minimum 10 f ceramic capacitor need to be connected close to the vtt terminal. the vttsen should be connected to the positive node of vtt output capacitor as a separated trace from the high- current line to the vtt pin. vddq power good (pg) the nb675 has power-good (pgood) output used to indicate whether the output voltage of the vddq regulator is ready or not. the pgood pin is the open drain of a mosfet. it should be connected to v cc or other voltage source through a resistor (e.g. 100k,). after the input voltage is applied, the mosfet is turned on so that the pgood pin is pulled to gnd before ss is ready. after fb voltage reaches 95% of ref voltage, the pgood pin is pulled high after a delay. the pgood delay time is 1ms. when the fb voltage drops to 85% of ref voltage, the pgood pin will be pulled low. vddq over current protection nb675 has cycle-by-cycle over current limiting control. the current-limit circuit employs a "valley" current-sensing algorithm. the part use the rds(on) of the low side mosfet as a current-sensing element. if the magnitude of the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the trip level is fixed internally. the inductor current is monitored by the voltage between gnd
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 15 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin and sw pin. gnd is used as the positive current sensing node so that gnd should be connected to the source terminal of the bottom mosfet. since the comparison is done during the high side mosfet off and low side mosfet on state, the oc trip level sets the valley level of the inductor current. thus, the load current at over- current threshold, ioc, can be calculated as follows: =+ inductor oc i i i _ limit 2 (13) in an over-current condition, the current to the load exceeds the current to the output capacitor; thus the output voltage tends to fall off. eventually, it will end up with crossing the under voltage protection threshold and shutdown. vtt over-current protection the vtt ldo has an internally fixed current limit of 1.8a for source operation, and 1.6a for sink. vddq over/under-voltage protection (ovp/uvp) nb675 monitors a resistor divided feedback voltage to detect over and under voltage. when the feedback voltage becomes higher than 115% of the target voltage, the controller will enter dynamic regulation period. during this period, the ls will off when the ls current goes to -1a, this will then discharge the output and try to keep it within the normal range. if the dynamic regulation can not limit the increasing of the vo, once the feedback voltage becomes higher than 130% of the feedback voltage, the ovp comparator output goes high and the circuit latches as the high-side mosfet driver off and the low-side mosfet turn on acting as an - 1a current source. when the feedback voltage becomes lower than 60% of the target voltage, the uvp comparator output goes high if the uv still occurs after 26us delay; then the fault latch will be triggered--- latches hs off and ls on; the ls fet keeps on until the inductor current goes zero. uvlo protection the nb675 has under-voltage lock-out protection (uvlo). when the vcc voltage is higher than the uvlo rising threshold voltage, the part will be powered up. it shuts off when the vin voltage is lower than the uvlo falling threshold voltage. this is non-latch protection. the part is disabled when the vcc voltage falls below 4.5v. if an application requires a higher under-voltage lockout (uvlo), use the en pin as shown in figure 9 to adjust the input voltage uvlo by using two external resistors. it is recommended to use the enable resistors to set the uvlo falling threshold (vstop) above 4.5v. the rising threshold (vstart) should be set to provide enough hysteresis to allow for any input supply variations. en comparator r up r down en nb675 in figure 9?adjustable uvlo thermal shutdown thermal shutdown is employed in the nb675. the junction temperature of the ic is internally monitored. if the junction temperature exceeds the threshold value (typical 150oc), the converter shuts off. this is a non-latch protection. there is about 25oc hysteresis. once the junction temperature drops to about 125oc, it initiates a ss. output discharge nb675 discharges all the outputs, including vddq, vttref and vtt when en2=low, or the controller is turned off by the protection functions (uvp & ocp, ocp, ovp, uvlo, and thermal shutdown). the part discharge the outputs using an internal 6 ? mosfet.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 16 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. application information setting the output voltage---without external compensation the nb675 can usually support different type of output capacitors, including poscap, electrolytic capacitor and also ceramic capacitors without external ramp compensation, the output voltage is then set by feedback resistors r1 and r2. as figure 10 shows. r1 r2 cap sw fb vo l c4 figure10?simplified circuit of pos capacitor first, choose a value for r2. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. typically, set the current through r2 at around 5-10ua will make a good balance between system stability and also the no load loss. then r1 is determined as follow with the output ripple considered: out out ref 12 ref 1 vvv 2 rr v ? ? =? (13) out v is the output ripple, refer to equation (23) other than feedback resistors, a feed forward cap c4 is usually applied for a better transient performance, especially when ceramic caps are applied for their small capacitance, a cap value around 100pf-1nf is suggested for a better transient while also keep the system stable with enough noise immunity. in case the system is noise sensitive because of the zero induced by this cap, add a resistor-usually named as r9 between this cap and fb to form a pole, this resistor can be set according to equation (16) as in the following section. setting the output voltage D with external compensation r1 r2 ceramic sw fb vo l r9 r4 c4 figure11?simplified circuit of ceramic capacitor if the system is not stable enough when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4. the output voltage is influenced by ramp voltage v ramp besides r divider as shown in figure 11. the v ramp can be calculated as shown in equation 7. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? -50k ? for r2, using a comparatively larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high. and the value of r1 then is determined as follow: 2 1 fb(avg) 2 out fb(avg) 4 9 r r= v r - (v -v ) r +r (14) the v fb(avg) is the average value on the fb, v fb(avg) varies with the vin, vo, and load condition, etc., its value on the skip mode would be lower than that of the pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) . if one wants to gets a better load or line regulation, a lower vramp is suggested, as long as the criterion shown in equation 8 can be met. for pwm operation, v fb(avg) value can be deduced from the equation below. 12 fb( avg) ref ramp 12 9 r//r 1 vvv 2r//rr =+ + (15)
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 17 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. usually, r9 is set to 0 ? , and it can also be set following equation 16 for a better noise immunity. it should also set to be 5 times smaller than r1//r2 to minimize its influence on vramp. 9 4sw 1 r 2c2f = (16) using equation 14 to calculate the r1 can be complicated. to simplify the calculation, a dc- blocking capacitor cdc can be added to filter the dc influence from r4 and r9. figure 12 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. with this capacitor, r1 can easily be obtained by using the simplified equation for pwm mode operation: ?? = + out ref ramp 12 ref ramp 1 (v v v ) 2 rr 1 vv 2 (17) cdc is suggested to be at least 10 times larger than c4 for better dc blocking performance, and should also not larger than 0.47uf considering start up performance. in case one wants to use larger cdc for a better fb noise immunity, combined with reduced r1 and r2 to limit the cdc in a reasonable value without affecting the system start up. be noted that even when the cdc is applied, the load and line regulation are still vramp related. r1 r2 ceramic sw fb vo l cdc r4 c4 figure12?simplified circuit of ceramic capacitor with dc blocking capacitor input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance and should be placed as close to the v in pin as possible. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv = ? (18) the worst-case condition occurs at v in = 2v out , where: out cin i i 2 = (19) for simplification, choose the input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose the input capacitor that meets the specification. the input voltage ripple can be estimated as follows: out out out in sw in in in iv v v(1) fc v v = ? (20) under worst-case conditions where v in = 2v out : out in sw in i 1 v 4f c = (21) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc = ? + (22) in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as:
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 18 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. out out out 2 sw out in vv v(1) 8f lc v = ? (23) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4. in the case of poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external ramp is not needed. a minimum esr value around 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated as: out out out esr sw in vv v(1)r fl v = ? (24) maximum output capacitor limitation should be also considered in design application. nb675 has an around 1.6ms soft-start time period. if the output capacitor value is too high, the output voltage can?t reach the design value during the soft-start time, and then it will fail to regulate. the maximum output capacitor value c o_max can be limited approximately by: o_max lim_avg out ss out c(i i)t/v =? (25) where, i lim_avg is the average start-up current during soft-start period. t ss is the soft-start time. inductor the inductor is necessary to supply constant current to the output load while being driven by the switched input voltage. a larger-value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger-value inductor will have a larger physical footprint, higher series resistance, and/or lower saturation current. a good rule for determining the inductance value is to design the peak-to- peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current, and that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated by: out out sw l in vv l(1) fi v =? (26) where i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current, where the peak inductor current can be calculated by: out out lp out sw in vv ii (1 ) 2f l v =+ ? (27) pcb layout guide 1. the high current paths (gnd, in, and sw) should be placed very close to the device with short, direct and wide traces. 2. put the input capacitors as close to the in and gnd pins as possible. 3. put the decoupling capacitor as close to the vcc and gnd pins as possible. place the cap close to vcc if the distance is long. and place >3 vias if via is required to reduce the leakage inductance. 4. keep the switching node sw short and away from the feedback network. 5. the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 6. keep the bst voltage path (bst, c3, and sw) as short as possible. 7. keep the in and gnd pads connected with large copper and use at least two layers for in and gnd trace to achieve better thermal performance. also, add several vias with 10mil_drill/18mil_copper_width close to the in and gnd pads to help on thermal dissipation. 8. four-layer layout is strongly recommended to achieve better thermal performance. note please refer to the pcb layout application note for more details.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 19 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. 9 sw 17 16 14 en2 pgnd vcc 13 pg vin 12 15 en1 19 vin 20 pgnd 21 pgnd 1 2 3 5678 4 to agnd 11 10 vout agnd kelvin connect to pgnd at vcc cap vin vout do not connect to pgnd here fb at least two layers should be applied for vin and pgnd and place >20 vias close to the part for a better thermal performance 18 pgnd agnd agnd --top layer --via --bottom layer --inner pgnd layer --inner layer2 --via for agnd pgnd bst lp figure 13?recommend layout recommend design example some design examples are provided below when the ceramic capacitors are applied: table 2?design example v out (v) cout (f) l ( h) r4 ( ? ) c4 (f) r1 (k ? ) r2 (k ? ) 1.05 22 x3 1.2 ns 220p 59 82 1.2 22 x3 1.2 ns 220p 100 102 1.35 22 x3 1.2 ns 220p 100 82 the detailed application schematic is shown in figure 14 when large esr caps are used and figure 15 when low esr caps are applied. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation board data sheets.
nb675 ?24v, high current sy nchronous buck converter nb675 rev. 1.0 www.monolithicpower.com 20 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical application en 1 fb bst vin pg sw en 2 nb675 pgnd vddq vcc vinldo vddqsen vtt vttsen agnd vttref vtt 22 f v in 4.7-22v 1.35v/10a 0.675v/2a 4.7 ? 220nf 499k ? 100k ? 1 f 82k ? 100k ? 22 fx3 220nf 1.2 h 22 f 10 f 10 f ceramic cap ns 220pf 499 figure 14 ? typical application circuit with low esr ceramic output capacitor v in =5-22v, v out =1.35v, i out =10a en 1 fb bst vin pg sw en 2 nb675 pgnd vddq vcc vinldo vddqsen vtt vttsen agnd vttref vtt 22 f v in 4.7-22v 1.35v/10a 0.675v/2a 4.7 ? 220nf 499k ? 100k ? 1 f 82k ? 100k ? 330 f 220nf 1.2 h 22 f 10 f 10 f poscap + figure 15 ? typical application circuit with large esr poscap output capacitor v in =5-22v, v out =1.35v, i out =10a
nb675 ?24v, high current sy nchronous buck converter notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. nb675 rev. 1.0 www.monolithicpower.com 21 1/14/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information qfn21 (3mmx4mm)

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